The Significance of Innovative Design Techniques in Fractional-N Phase Locked Loops

In the realm of wireless communication, radar systems, and beyond the 5G era, the performance of fractional-N phase locked loops (PLLs) plays a crucial role. Scientists from Tokyo Tech have recently introduced two innovative design techniques that could potentially revolutionize the way PLLs function. These techniques are aimed at reducing fractional spurs, the unwanted signals that often hinder the performance of PLLs in various modern applications.

From self-driving vehicles to target tracking systems, many emerging technologies heavily rely on the speed and accuracy of wireless data transceivers and radar systems. PLLs are essential components in these systems, responsible for synthesizing, modulating, and synchronizing oscillating signals. Any errors or unwanted signals in PLLs can greatly impact the overall performance of these technologies.

Fractional-N PLLs are known for their excellent resolution and flexible frequency control, but they are often plagued by jitter and fractional spurs. Jitter refers to deviations in timing, while fractional spurs are unwanted signals that result from periodic errors. These issues can lead to degraded phase noise and affect the efficiency of PLLs in various applications.

The research team from Tokyo Tech, led by Professor Kenichi Okada, introduced two groundbreaking design techniques to address the challenges faced by fractional-N PLLs. The first technique involves using a cascaded-fractional divider to split the frequency control word (FCW) into two values that are far from integers. This approach aims to filter out high-frequency components naturally, without the use of digital pre-distortion techniques.

The second technique focuses on implementing a pseudo-differential digital-to-time converter (DTC) to avoid the limitations of standard DTC designs. By utilizing two half-range DTCs with symmetric components in a differential operation, the researchers were able to cancel out non-linearities and achieve lower levels of fractional spurs.

The research team tested their innovative design techniques by implementing a digital PLL using a 65 nm CMOS process. The results were promising, with a significant reduction in integrated PLL jitter from 243.5 fs to 143.7 fs. By suppressing fractional spurs and incorporating the cascaded fractional divider and pseudo-differential DTC, the researchers were able to achieve exceptional performance without the need for complex DPD technology.

The introduction of these innovative design techniques has the potential to bring about significant improvements in various applications that rely on fractional-N PLLs. From wireless communication to autonomous vehicles, the advancements in PLL performance could pave the way for more efficient and reliable technologies in the near future. Prof. Okada and his team’s work could potentially set a new standard in the design and implementation of PLLs, leading to enhanced performance and functionality across different industries.


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